1. Field of the Invention
The present invention relates to a booster for boosting a supplied voltage, an IC card having the same, and electronic equipment having the same. The present invention particularly relates to a booster for reducing a current peak and improving boosting efficiency, an IC card having the same, and electronic equipment having the same.
2. Description of the Related Art
Recently, a non-contact IC (integrated circuit) card has received attention as a recording medium. The non-contact IC card includes an EEPROM (Electrically Erasable Programmable Read Only Memory), receives by an antenna a high-frequency signal transmitted from a terminal equipment, and generates electricity for internal use.
FIG. 1 is a schematic diagram showing the relationship of voltages supplied to circuits in the non-contact IC card.
As shown in FIG. 1, a non-contact IC card 101 is provided with an RF circuit 102, which extracts a data component from a signal received by the antenna and generates an internal source voltage Vdd. A central processing unit (CPU) 103, an I/O circuit 104, and a peripheral circuit 105, which are operated by the internal source voltage Vdd, are further provided. The IC card 101 includes an EEPROM 106 for storing data and a charge pump 107 for generating a voltage Vpp, which is used for writing and deleting data in the EEPROM 106. Additionally, a decoder and the like in the EEPROM 106 are operated by the internal source voltage Vdd. Moreover, the IC card 101 is provided with a voltage regulator 108 for reducing the internal source voltage Vdd to a voltage for charge pump Vcp, which is applied to the charge pump 107, and a ring oscillator 109 for dividing the voltage for charge pump Vcp to produce a clock signal (frequency: about 4 to 8 MHz) of the charge pump 107.
Further, normally, the internal source voltage Vdd is set at about 2.2 to 3.3 V, the voltage for charge pump Vcp is set at about 2.0 to 2.5 V, and the voltage Vpp is set about 12 to 13 V.
Also, the magnitude of electricity (internal source voltage Vdd) generated by receiving a high-frequency signal is determined by a distance between the terminal equipment and the non-contact IC card, the shape of the antenna, and the like. The efficiency of generating electricity is not so high. Hence, the IC card 101 includes a security circuit 110 for suspending the operation of the CPU 103, the I/O circuit 104, the peripheral circuit 105, and the like to prevent malfunction thereof in the case of a drop in the internal source voltage Vdd.
A clock signal supplied to the CPU 103 is extracted from signals received in the RF circuit 102, and the clock signal is inputted as an operating clock signal (control clock signal) to the I/O circuit 104, the peripheral circuit 105, the security circuit 110, and the voltage regulator 108 as well as the CPU 103.
FIG. 2 is a circuit diagram showing an example of a conventional charge pump.
In the conventional charge pump, for example, a plurality of transistors Tr100, Tr101, Tr102, Tr103, Tr104, and the like are connected in series. A voltage for charge pump Vcp is supplied to the gate and source of the transistor Tr100. Further, capacitors C101, C102, C103, C104, and the like each have a terminal connected to each node provided between the adjacent transistors. Inverters IV101, IV102, IV103, IV104, and the like are respectively connected to the other terminals of the capacitors. A clock signal CLK oscillated by the ring oscillator 109 is inputted to the inverters IV 101, IV103, and the like, and an inverted signal CLKB of the clock signal CLK is inputted to the inverters IV102, IV104, and the like. Therefore, the inverters IV101, IV103, and the like are simultaneously driven and the inverters IV102, IV104, and the like are simultaneously driven. Additionally, the clock signal CLK in FIG. 2 corresponds to the clock signal CLK shown in FIG. 1.
Moreover, Japanese Patent Laid-Open Publication No. Hei 2-62796 discloses a booster in which inverters are connected in series. FIG. 3 is a circuit diagram showing the booster disclosed in this publication.
In the booster of the publication as well, a plurality of transistors Tr110, Tr111, Tr112, Tr113, Tr114, and the like are connected in series, and a source voltage is supplied to the gate and source of the transistor Tr110. Also, capacitors C111, C112, C113, C114, and the like each have a terminal connected to each of the nodes. Each of the nodes is provided between the adjacent transistors. Inverters IV111, IV112, IV113, IV114, and the like are connected to the other terminals of the capacitors. Here, the inverters IV111, IV112, IV113, IV114, and the like are connected in series, and a clock signal CLK is inputted to the inverter IV111 on the first stage. Therefore, a signal in opposite phase with the clock signal CLK is inputted to the transistors Tr111, Tr113, and the like, and a signal in phase with the clock signal CLK is inputted to the transistors Tr112, Tr114, and the like. Hence, the inverters IV111, IV113, and the like are simultaneously driven and the inverters IV112, IV114, and the like are simultaneously driven. However, the inverters connected in series cause delay of a clock signal, so that the transistors are gradually shifted from one another in operational timing. Additionally, the clock signal CLK in FIG. 3 corresponds to the clock signal CLK shown in FIG. 1.
However, in the conventional charge pump shown in FIG. 2, about a half of the transistors are driven by one clock signal, so that a clock driver handles heavy load. A large number of clock drivers are simultaneously operated, resulting in an extremely high peak of source current on the rising of a clock signal. Namely, when source current has an extremely high peak, electricity supplied to the voltage regulator 108 rapidly increases at the moment and electricity supplied to the other circuits rapidly decreases. Although the security circuit 110 can detect a relatively mild reduction in electricity to prevent malfunction of the other circuits, the security circuit 110 cannot detect the above rapid reduction to suspend the operation of the circuit such as the CPU 103. For this reason, in the case of a high peak of source current, malfunction is likely to occur in the CPU 103 and the like.
Meanwhile, in the conventional booster shown in FIG. 3, the inverters IV 111 and the like are connected with delays and driving function. Hence, when the delay is reduced by shortening a clock period to shorten boosting time, current of the following stage is superposed to that of the previous stage. Consequently, the amount of current increases with later stages. Thus, a peak of current cannot be sufficiently reduced and is increased with the number of stages.
Furthermore, Japanese Patent Laid-Open Publication No. Hei 11-164545 discloses a charge pump in which a plurality of charge pump stages are provided and are shifted from one another in operation. Although a current peak is smaller than that of the precedent applications, the reduction is not sufficient. Moreover, a high period coincides with that of a clock signal on the following stage, so that charging and discharging times cannot be sufficiently obtained, resulting in lower booster efficiency.
An object of the present invention is to provide a booster being capable of preventing malfunction of other circuits in a non-contact IC card by reducing a current peak, an IC card having the same, and electronic equipment having the same.
According to the present invention, a booster comprises first to k-th (k is an even number) transistors connected to one another in series, first to k-th capacitors each having an end connected to the gate and source of each of the first to k-th transistors, and a clock driver which supplies clock signals out of phase with one another to the other ends of the first to k-th capacitors. The clock driver simultaneously supplies low-level clock signals to two or more adjacent capacitors out of the first to k-th capacitors.
In the present invention, the clock driver simultaneously supplies low-level clock signals to the two or more adjacent capacitors, so that two or more low-level nodes exist on the following stage and later of the transistor connected to the capacitor receiving a high-level clock signal. Therefore, for example, assuming that the transistor transmits ten charges to the node on the following stage, the transistor being connected to the capacitor where a high-level clock signal is supplied, the transmission of the ten charges turns on the transistor on the following stage and some of the ten charges are transmitted to a node on the still following stage. As a result, each of the nodes quickly increases in potential, adverse effect such as backflow of a current is immediately prevented, and boosting efficiency is improved.
In the clock driver in the present invention, when the first to k-th capacitors are divided from the first capacitor into groups, each constituted by n capacitors (n is a submultiple of k), clock signals with n phases may be supplied to the first to n-th capacitors, in the clock signals with n phases, high periods do not overlap one another and the rising timings are shifted in order of the first to n-th capacitors, and clock signals with n phases may be supplied to each of the other groups. The clock signals are delayed by a fixed amount from the above n-phase clock signals.
In this case, to the first to n-th capacitors, the clock signals with n phases are supplied in which high periods do not overlap one another and the rising timings are shifted in order of the first to n-th capacitors. Hence, regarding the transistors connected to such capacitors, the gate and source of the transistor increase in potential when a transistor on the previous stage is turned on. Thereafter, such an increase in potential is repeated in the (n+1)-th to k-th transistors. Consequently, the clock signals with k phases are different from one another in phase, so that charging and discharging times can be sufficiently obtained for each of the nodes and boosting efficiency can be improved. Further, the clock signals are shifted from one another in rising timing, so that it is possible to reduce a current peak and prevent malfunction of the other circuits that is caused by a current peak.
Additionally, for example, in the case of application for a non-contact IC card or the like, it is possible to prevent malfunction in the other circuits that is caused by a current peak.